1. Field of Invention
The present invention relates to a circuit for providing a crystal oscillator circuit with low power consumption, and particularly relates to an oscillator circuit including an amplifier circuit and an electronic apparatus including the oscillator circuit.
2. Description of the Related Art
For a portable apparatus, such as a watch or mobile phone, long time operation without charging and reduction in frequency of charging a built-in battery are desired. Accordingly, there is a growing demand for reducing drive power of an oscillator circuit including a piezoelectric device, such as a crystal resonator, used for the portable apparatus and significantly reducing power consumption of the oscillator circuit in standby mode (i.e., when the oscillator circuit is oscillating in unloaded condition).
FIG. 3 shows a typical oscillator circuit including a crystal resonator, including: a CMOS inverter IV01 as an inverting amplifier; a crystal resonator X2 connected between the input terminal XCIN and output terminal XCOUT of the CMOS inverter IV01; a capacitor providing a load capacitance Cg connected between the input terminal XCIN of the CMOS inverter IV01 and the power supply terminal Vss of a ground potential; and a capacitor providing a load capacitance Cd connected between the output terminal XCOUT of the CMOS inverter IV01 and the power supply terminal Vss of the ground potential.
The CMOS inverter IV01 includes a CMOS inverter consisting of a PMOS transistor PM11 and an NMOS transistor NM11 connected in series between a first power supply terminal and a second power supply terminal supplied with a power supply voltage Vdd and the ground potential, respectively, and a feedback resistor Rf. Drive current adjusting resistors r1 and r2 limit drive current for exciting the crystal resonator X2, the resistor r1 being connected between the source of the PMOS transistor PM11 of the CMOS inverter IV01 and the first power supply terminal, the resistor r2 being connected between the NMOS transistor NM11 of the CMOS inverter IV01 and the second power supply terminal.
In recent years, there is a demand for reducing power consumption of an oscillator circuit included in a portable apparatus or the like. In order to meet this demand, drive current of a crystal resonator of the oscillator circuit needs to be reduced. In order to do this, reducing the transconductance Gm of a CMOS inverter of the oscillator circuit may be appropriate. But, reducing the transconductance Gm may reduce the oscillation margin of the oscillator circuit.
The oscillation margin M of the oscillator circuit is given by the following equation (1):M={|−Gm|/(ω2Cg·Cd)}*(1/R1(max))=RL/R1(max)  Eq. (1)where ω is angular frequency of oscillation frequency, RL is negative resistance, R1(max) is the maximum value of the effective resistance R1 of the crystal resonator, and the oscillation margin M needs to be 5 or more.
Since the effective resistance R1 of the crystal resonator is to be determined in order to downsize the crystal resonator, the effective resistance R1 cannot be reduced too much. So, in order to maintain the oscillation margin M of the oscillator circuit while reducing the Gm, the load capacitances Cg and/or Cd of the capacitors providing the external load capacitance of the CMOS inverter should be reduced. So, in order to achieve this, the crystal resonator of the oscillator circuit needs to have a load capacitance CL meeting the requirement of reducing power consumption of a built-in IC, such as a microcomputer. In view of this, the applicant has already proposed the reduction of the load capacitance CL, or reduced CL (3-5 pF) with respect to the load capacitance CL of 12.5 pF for a conventional crystal resonator (JP-A-2008-205658).
However, reducing the load capacitance CL makes noticeable a problem of the capacitance tolerance of load capacitance CL and the frequency deviation Δf of oscillation frequency. For example, the oscillation frequency stability Δf (in ppm) when the load capacitance CL varies by ΔC (±5%) which is within a normal capacitance tolerance is 7.3 ppm with a load capacitance CL of 12.5 pF and ΔC of 1.25 pF; 13.2 ppm with a load capacitance CL of 6 pF and ΔC of 0.6 pF; and 20.5 ppm with a load capacitance CL of 3 pF and ΔC of 0.3 pF. This means that the load capacitance CL of 3 pF exhibits 2.8 times as much frequency deviation as the conventional load capacitance CL of 12.5 pF. So, in order to reduce the load capacitance CL (achieve reduced CL), the oscillation frequency stability with respect to the capacitance tolerance of the load capacitance CL needs to be improved.
FIG. 4 shows an equivalent circuit of the circuit in FIG. 3 between the input/output terminals XCIN and XCOUT on the crystal resonator side. The crystal resonator X2 and the load capacitance CL are connected in series. The crystal resonator is expressed as a circuit in which a serial resonance circuit of an inductance L1, a capacitance C1 and a resistance R1 that equivalently represents a mechanical resonance due to a piezoelectric effect and an inter-electrode capacitance C0 are connected in parallel. Also, various stray capacitances due to a CMOS semiconductor substrate, signal wires and the like exist between the input/output terminals XCIN and XCOUT. Denoting a combined stray capacitance of these stray capacitances by Cs, the load capacitance CL is a parallel connection of the stray capacitance Cs and the external capacitances Cg and Cd connected in series as shown in FIG. 5.
Accordingly,CL=Cs+Cg*Cd/(Cg+Cd)  Eq. (2).
Selecting external capacitors Cg and Cd matching with the oscillation frequency so that the CL will be 2-6 pF that meets the relation of (2) can improve the oscillation frequency stability. Specifically, since the load capacitance CL is the sum of the stray capacitance Cs and the external capacitance Cext {=Cg*Cd/(Cg+Cd)}, selecting the value of the external capacitance Cext to be corresponding to the difference between the load capacitance CL and the stray capacitance Cs may satisfy the equation (2), meaning that the load capacitance CL of the crystal resonator may match with the load capacitance on the oscillator circuit side with respect to the crystal resonator.
FIG. 6 shows a relation between the drive current and load capacitance CL of the crystal oscillator circuit. As seen from FIG. 6, the drive current significantly decreases as the load capacitance CL decreases. For example, with a conventionally employed load capacitance of 12.5 pF, the drive current is about 1.5 μA, whereas, with a load capacitance of 2.2 PF, the drive current is 0.073 μA, reduced to about 5%. Thus, reducing the load capacitance CL contributes to reduced power consumption of the crystal oscillator circuit, and furthermore contributes to reduced power consumption of an electronic apparatus including the crystal oscillator circuit.
When the drive current of the crystal oscillator circuit is less than 0.1 μA (100 nA), the output voltage (Vout) is less than 10% of the supply voltage (Vpp) (i.e., Vout<0.1 Vpp), and since the supply voltage is about 1-3 V, the output voltage (Vout) is less than 0.1-0.3 V. FIG. 7 shows an example of using a comparator as a circuit connected to the output side of the crystal oscillator circuit. The circuit on the crystal oscillator circuit side shown in FIG. 7 is essentially similar to the circuit in FIG. 3, including a crystal resonator 11, a CMOS inverter 12 and a constant current source 13. The output Vout1 of the crystal oscillator circuit is analog signal (near-sinusoidal wave signal), which is converted into digital signal (rectangular wave signal) output Vout2 through a comparator 14. When the output Vout1 of the crystal oscillator circuit is more than 0.1-0.3 V, the comparator 14 operates properly, providing comparator output at a frequency (f0) corresponding to the output frequency (f0) of the crystal oscillator circuit. However, when the output Vout1 is less than about 0.1 V, the difference between two input voltages of the comparator may be too small to generate proper comparator output Vout2 (clock signal). This means that since the output of the crystal oscillator circuit has too low amplitude, the circuit connected to the crystal oscillator circuit cannot perform accurate information transmission for the output signal of the crystal oscillator circuit. Particularly, when the load capacitance CL is further reduced so that the drive current of the crystal oscillator circuit is about 50 nA, the output Vout1 of the crystal oscillator circuit exhibits further lower amplitude waveform of about 0.05 Vpp, which prevents the comparator 14 from outputting any output clock signal Vout2.
In view of the above, it is an object of the present invention to provide a circuit that provides output signal so that various next-stage circuits connected to the output side of a crystal oscillator circuit operate properly even when the drive current of the crystal oscillator circuit significantly decreases to less than 100 nA to cause the output voltage of the crystal oscillator circuit to be reduced to less than about 0.1 Vpp. That is, the invention relates to an oscillator circuit including an amplifier circuit and an electronic apparatus including the oscillator circuit.